AMBA APB 2.0 Presented By Aditya Dayal ITM University, Gwalior

Introduction to the AMBA Buses: The Advanced Microcontroller Bus Architecture (AMBA) specification defines on chip communications standard for designing high-performance embedded microcontrollers. The distinct buses are defined within the AMBA specification: Advanced High-performance Bus (AHB) Advanced System Bus (ASB) Advanced Peripheral Bus (APB) Advanced eXtensible Interface (AXI)

HISTORY OF AMBA PROTOCOLS Performance 1999 2003 1995 Time APB ASB AHB AXI

APPLICATIONS Mobile segment Smart phones Portable Audio Portable Media Voice phone Digital camera Home segment DVD Players Set top box Portable gaming HDTV

Overview of the AMBA family specifications AHB (Advanced high-performance bus) Highest performance bus in the AMBA family before AXI Suitable for medium complexity and performance connectivity solutions AHB Lite Subset of the full AHB spec Intended for use in designs where only a single master is used ASB (Advanced system bus) The AMBA ASB is for high-performance system modules ASB also supports the efficient c onnection of processors, on-chip memories and off-chip external memory interfaces with low-power peripherals. APB(Advanced peripheral bus) General purpose I/O Register based peripherals such as timers,interrupt controllers,UART etc. Connected to system bus via a bridge, helps to reduce system power consumption Easy to interface to, with little logic involved .

AMBA 2.0 application space Serves as a frame work for Soc designs System-on-a-chip(SOC) designs On-chip bus for ARM processors

A typical AMBA-based microcontroller: High-bandwidth memory interface High-performance ARM processor PIO DMA bus master High-bandwidth on-chip RAM Timer UART keypad B R I D G E AHB/ASB APB Figure:The APB in a typical AMBA system

AMBA APB: The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. The AMBA APB is used to interface to any peripherals which are low bandwidth and do not require the high performance of a pipelined bus interface. Low power Latched address and control Simple interface Suitable for many peripherals

AHB vs APB

Micro architecture -Master APB bridge PRDATA PADDR PWDATA System bus slave interface Read data reset clock PRESETn PCLK PSEL1 PSEL2 PSELn PENABLE PWRITE SELECTS STROBE ADDRESS AND CONTROL WRITE DATA

Micro architecture -SLAVE APB slave PADDR PWDATA PRDATA SELECT STROBE ADDRESS AND CONTROL RESET CLOCK WRITE DATA PSELx PENABLE PRESETn PCLK PWRITE READ DATA

APB signals

APB signals (cont’d)

APB FSM IDLE PSELx=0 PENABLE=0 SETUP PSELx=1 PENABLE=0 ENABLE PSELx=1 PENABLE=1 transfer No transfer No transfer transfer

APB FSM State diagram of peripheral bus activity IDLE The default state for the peripheral bus SETUP The bus moves into this state when a transfer is required The bus remains in the SETUP state for one clock and always move to the ENABLE state PSELx is asserted ENABLE PENABLE is asserted the address, write and select signals all remain stable during SETUP->ENABLE

Write Transfer Timing

Write cycle Write starts with address, write data, write signal and select signal, all changing after the rising edge of the clock After the following clock edge the enable signal PENABLE is asserted , and this indicates that the ENABLE cycle is taking place To reduce power consumption the address and the write signal will not change after a transfer untill the next access occurs

Read Transfer Timing

Read cycle The timing of the address,select and strobe signals are all the same as for the write except PWRITE Read ,the slave must provide the data during the ENABLE cycle Data is sampled on the rising edge of clock at the end of the ENABLE cycle

Thank you